As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a Fin Field Effect Transistor (FinFET). FinFET devices typically include semiconductor fins with high aspect ratios and in which channel and source/drain regions are formed. A gate is formed over and along the sides of the fin structure (e.g., wrapping) utilizing the advantage of the increased surface area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices.
The line edge roughness of the fin structure can affect the performance of the transistors. To ensure the line edge roughness is maintained within a range desired for downstream processing, a surface measurement technique can be performed to obtain roughness information of the fin structure. However, with the decreasing in scaling, new challenges are presented.